SRAM memory arrays are well known in the art. They are characterized by a fast write time and a fast read time. However, they suffer from the disadvantage of being volatile and low density. Flash memory arrays are also well known in the art. They offer the advantage of high density as well as non-volatility. However, they suffer from the disadvantage of low erase and programming speed as well as low read speed. Heretofore, the prior art teaches the use of an SRAM memory array having as many storage locations as a flash memory array to "shadow" the memory array. Data would be stored to and read from the SRAM memory array. During the time that the memory array is not being accessed, the contents of the SRAM memory array would be transferred to the accompanying flash memory array for long-term non-volatile storage. It should be recognized, however, that in such an arrangement, should access be required from the SRAM memory array during the time that it is transferring its contents to the flash memory array, the entire memory circuit would not be accessible by the external environment. In such an event, the memory circuit would be busy.
Further, another disadvantage of this prior art memory device is that a large amount of memory is devoted to the SRAM which is low density since there has to be as many SRAM memory cells as there are flash memory cells. Accordingly, it is desirable to reduce the number of SRAM memory cells and yet at the same time provide higher periods of accessibility for the entire memory circuit.